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Digital Logic MCQ BCA First Semester 2023 Batch

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Which gates in Digital Circuits are required to convert a NOR-based SR latch to an SR flip-flop?

Two 2 input AND gates

Two 3 input AND gates

Two 2 input OR gates

Two 3 input OR gates

What will be the output from a D flip-flop if the clock is low and D = 0?

No change

Toggle between 0 and 1

The result “X + XY =X” follows which of these laws?

Consensus law

Distributive law

Duality law

Absorption law

The full form of PLD is_______

Programmable Load Devices

Programmable Logic Data

Programmable Logic Devices

Programmable Loaded Devices

What value is to be considered for a “don’t care condition”?

Either 0 or 1

Any number except 0 and 1

How many possible outputs would a decoder have with a 6-bit binary input?

128

When output will go high in AND Gate?

If all inputs are high

If any input is high

If all inputs are low

If any input is low states

What must be used along with synchronous control inputs to trigger a change in the flip flop?

Clock

Previous output

Which of the following gives the correct number of multiplexers required to build a 32 x 1 multiplexer?

Two 16 x 1 mux

Three 8 x 1 mux

Two 8 x 1 mux

Three 16 x 1 mux